In the conventional technology, connection between integrated circuit (IC) chips and external electric circuit is often realized by using a metal-wire-bonding method.
However, with the reduction of the feature size of IC chips and the expansion of the scale of IC, the wire-bonding method is no longer applicable. Wafer-level chip scale packaging (WLCSP) technology refers to a method in which a whole wafer is packaged and tested before being cut into individual complete chips. Therefore, in the WLCSP technology, the size of the packaged chip is the same as the size of the die. The WLCSP technology has subverted the traditional packaging modes such as ceramic leadless chip carrier, organic leadless chip carrier, etc., and has complied with the increasing market demand on light, small, short, thin, and low-cost microelectronic products. The size of chips packaged by the WLCSP technology reaches a high degree of miniaturization. In the meantime, the cost of the chips is significantly reduced as the size of chips decreases while the size of the wafers increases. The WLCSP technology may be a technique to integrate IC design, wafer fabrication, packaging, and testing together. The WLCSP technology is currently a hot topic in the field of packaging and represents the trend of future development.
FIG. 1 shows a schematic cross-section view of an exemplary chip structure packaged by a WLCSP method in the current technology. Referring to FIG. 1, the chip structure packaged by the method in the current technology includes a semiconductor substrate 1, a conductive metal pad 11 formed on the semiconductor substrate, an under bump metal layer 3 formed on the conductive metal pad 11, and a bump structure 2 located on the top of the under bump metal layer 3.
However, in such a structure, the bump structure 2 may have a relatively small contact region with the under bump metal layer 3, thus resulting in relatively weak bonding strength of the packaged structure. Therefore, the mechanical stability of the packaged structure may also be reduced. For example, the bump structure 2 and the under bump metal layer 3 may be partially or even completely separated from each other and, in the meantime, the electric conductivity and thermal conductivity of the entire packaged structure may also be affected.
The disclosed method and structure for wafer-level packaging is directed to solve one or more problems set forth above and other problems.